chipsalliance / caliptra-rtl
HW Design Collateral for Caliptra RoT IP
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HW Design Collateral for Caliptra RoT IP
Verilator open-source SystemVerilog simulator and lint system
OpenTitan: Open source silicon root of trust
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Common SystemVerilog components
AXI Adapter(s) for RISC-V Atomic Operations
A minimal GPU design in Verilog to learn how GPUs work from the ground up