adam-maj / tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
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A minimal GPU design in Verilog to learn how GPUs work from the ground up
Verilator open-source SystemVerilog simulator and lint system
OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
HW Design Collateral for Caliptra RoT IP
APB Logic
BaseJump STL: A Standard Template Library for SystemVerilog
RSD: RISC-V Out-of-Order Superscalar Processor
Simple single-port AXI memory interface
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Common SystemVerilog components