lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
100 Days of RTL
SystemVerilog modules and classes commonly used for verification
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication