cindychip Follow

cindychip Follow

cindychip

Follow

1 follower · 0 following · 2

Highlights

Arctic Code Vault Contributor

Popular repositories

CS250_syn_report

Verilog
opentitan

Forked from lowRISC/opentitan

OpenTitan: Open source silicon root of trust

SystemVerilog

905 contributions in the last year

Activity overview

Contributed to lowRISC/opentitan, eunchan/opentitan, lowRISC/ibex and 5 other repositories

Contribution activity

November 2020

Created 14 commits in 1 repository

lowRISC/opentitan 14 commits

Created a pull request in lowRISC/opentitan that received 4 comments

[doc] update DV and DOC wording from sanity to smoke

For all the IPs and top-level dv, this commit update the word from sanity to smoke. For OTBN, I only changed under the dv/uvm folder. @rswarbrick …

+527 −527 • 4 comments

Opened 13 other pull requests in 1 repository

lowRISC/opentitan

12 merged 1 open

[dv/alert_esc_agent] Corner case timing alignment Nov 10
[fpv] fix regen regression failure Nov 10
[dv/otp] Fix status bit order Nov 9
[dv/alert] Support async mode in device mode Nov 6
[dv/alert_test] Add alert_test IP level automation test Nov 6
[dv/dvsim] Fix -c option compile error Nov 5
[fpv] Fix dv-verified IPs' fusesoc dependency issue and add them back to nightly regression Nov 5
[dv/otp] Pwr_otp interface cleanup Nov 4
[doc] Add lint requirements to V1 checklist Nov 4
[otp] Fix CI private compile error Nov 3
[lint] Add lint checking to FPV tb Nov 3
[lint] Add IPs to DV lint Nov 3
[fpv] JG script improvement Nov 3

Reviewed 14 pull requests in 1 repository

lowRISC/opentitan 14 pull requests

[doc] update DV and DOC wording from sanity to smoke Nov 11
[lc_ctrl] Initial version of the life cycle controller spec Nov 10
[alert_handler] Add buffer region after regs with parametric size Nov 9
[dv common] Minor enhancements to dv_reg_block Nov 6
[otp_ctrl] Reverse bitslice assignment to the status register Nov 6
[otp_ctrl] Change state_q assignment to ease debugging Nov 5
[dv/common] Fix regwen issue Nov 5
[kmac] Fix FPV testbenches Nov 4
[otp_ctrl/otbn/aes] Fix alert test register enumeration order Nov 4
[sw] Minor fix for crt code Nov 4
[pattgen, dv] Support V1 for pattgen Nov 3
[dv/xbar] Improve chip level xbar performance Nov 3
[lint] Add IPs to DV lint Nov 3
[fpv] alert_rx/tx updates Nov 2

Created an issue in lowRISC/opentitan that received 2 comments

[alert] alert_test connection question

Hi Michael, I wonder if there is a connection issue within alert_test register. Here is my sequence in otp_ctrl: Use TLUL interface write alert_test…

2 comments

You can’t perform that action at this time.